PCIe 4.0 will double interconnect performance bandwidth and be better poised for use in mobile and IoT applications.
SAN FRANCISCO—PCI Express (PCIe), the bus standard that already drives many internal computer components from graphics card to storage devices, is already fast and powerful. But it could soon be getting even better.
Version 4.0 of the PCIe specification, which will introduce greatly increased speeds as well as other improvements intended to make it viable in a wider range of applications, is slated to be released in early 2017.
PCIe 4.0 will essentially double the interconnect performance bandwidth of the current 3.0 specification, from 8 gigatransfers per second (GTps) to 16GTps. In addition, it introduces new technologies to enhance power efficiency: the use of an L1 substate that drastically lowers power use in idle mode; half-swing and quarter-swing, which cut power consumption by 400mV and 200mV, respectively; and high-speed data transfer bursts with minimum idle power.
As with previous generations of PCIe, PCIe 4.0 will be fully backward-compatible, so devices designed for earlier specifications will still operate correctly with the new technology. It is also expected that the next generation of computer processors will offer support for it, though the two announced this week—Intel’s 7th Generation Core and AMD’s Zen—will likely be excluded, as the first products using them will be released before the specification is finalized.
Speaking with PCMag.com at the Intel Developer Forum (IDF) here this week, Al Yanes, president and chairman of the PCI-SIG, which maintains the PCIe specification, said these changes will make PCIe 4.0 considerably more scalable and thus better suited to applications ranging mobile platforms to desktop computers to servers. This could help improve mobile penetration for PCIe, which to date has been slow.
“There’s at least one or two solutions,” Yanes said, but “I’d like to have more. We’re trying to evangelize a bit better on our low power [usage in 4.0]. Flash, NVMe plays well; storage, I think we kind of got that one. So I think mobile is the spot.”
Yanes also stated that he “[hasn’t] seen a lot of Internet of Things solutions out there yet,” but that could change. “We want to be well positioned for that, and we think we are with the idle power.”
Whatever the case, Yanes anticipates little lag time once the specification becomes available. “We think there will be more products sooner, when the [PCIe 4.0] spec is released,” Yanes said, when asked about the new specification’s adoption rate, but warned about the importance of doing things in the right order. “We learned in Gen 2 that you need to validate the hardware; that blesses the spec, then you release the spec.”
Although PCIe 4.0 isn’t even out yet, 5.0 is already on PCI-SIG’s future roadmap, and Yanes anticipates another big performance boost from it—and perhaps more than one. “The fact is, some of the Ethernet has gone to 25GB,” Yanes said. “Can you get to 32GB? Maybe you have two different specifications. You have to slice and dice it.”
Yanes was unable to specify a date as to when users would see 5.0 arrive. But does he expect it to be seven years, the same as the amount of time between the release of PCIe 3.0 and 4.0? He said, “I hope it’s not that long.”
